A phase-locked loop (PLL) is, by nature, a closed-loop frequency control component that operates based on the phase difference between input and output signal of a voltage-controlled oscillator (VCO). PLL circuits can be used to generate an output clock signal whose phase is related to the phase of an input reference clock signal. More advanced PLLs, such as a clock-data recovery PLL (CDR PLL), are often used in high speed serial interface (HSSI) circuits. In addition to generating an output clock signal with the desired frequency based on the reference clock signal, the CDR PLL also tracks the data signal to ensure that the edge of the output clock signal is always in the middle of data eye of the data signal.
However, the data signal and the reference clock signal are inherently independent of each other. As such, CDR PLL circuits that track and align both data and reference clock signals with the output clock signal are complicated. Hardware design engineers rely on simulation models to gradually build up a system such as a CDR PLL circuit and to verify its functionality. This process presents several challenges, resulting from both the presence of signal noise in the data and reference clock signals and the lack of fast and reliable simulation models that can provide sufficient abstraction with short runtime.
In particular, a special situation called a race condition may occur when a data signal edge and a reference clock signal edge arrive simultaneously. In such situations, the desired simulation model must be able to produce glitch-free stable signal that are independent of event sequences. In addition, it has been difficult to model certain signal noise present in a CDR PLL circuit because a PLL is a mixed-signal component in which all analog transitions happen on the continuous time domain, whereas known simulators are driven by discrete events. It is difficult to customize the desired simulation model for an analog block while retaining enough system-level abstraction and overall accuracy.
Lastly, the ability to recover from a noisy reference clock signal or a noisy data signal quickly and efficiently (in terms of required computing resources during simulation) is extremely valuable. When jitter or parts-per-million (PPM) error are present, measurement of both the reference clock signal and the data signal may become unreliable. The desired simulation model should be able to simulate physical hardware behavior and efficiently estimate clock frequency and phase in a timely and accurate manner.
Existing simulation models emulate data tracking by fixing the edge of the reference clock at the middle of the data eye, which is an inaccurate representation of real data tracking behavior. Furthermore, known simulation models require a tradeoff between supporting complex simulation features and fast simulation runtime.